The annual Global IC Fabs and Facilities Report documented 27 new semiconductor manufacturing facilities announced in the past twelve months, marking a structural shift in foundry geography but revealing capital efficiency warnings beneath the expansion headline. Total announced capex across the cohort reached $420 billion, yet capex per wafer of monthly capacity climbed to $18,200—a 34% increase from the prior cycle peak in 2018 and the highest density on record.

The buildout spans eleven countries, with the United States accounting for nine facilities backed by CHIPS Act subsidies, Taiwan adding four despite geopolitical pressure, and Japan securing three through joint ventures with TSMC and Rapidus. Europe captured four sites under the European Chips Act framework, while Southeast Asia—primarily Malaysia and Vietnam—added five packaging and test facilities rather than leading-edge logic. India announced two fabs, neither yet funded beyond memoranda of understanding. The geographic dispersion reflects subsidy arbitrage more than end-market proximity; 63% of announced capacity targets trailing-edge nodes above 28nm, serving automotive and industrial customers with mandated domestic sourcing.

Capex density peaked because advanced nodes demand more extreme ultraviolet lithography tools at $380 million per unit, cleanroom specifications requiring 40% higher construction costs per square meter, and yields on 3nm and below running 15-22 percentage points below 7nm at comparable production maturity. The report noted that only six of the 27 facilities target leading-edge logic below 5nm, with the remainder split between mature nodes and compound semiconductors. TSMC's Arizona fab, the largest single project at $40 billion, will produce 20,000 wafers per month at full capacity in late 2025—equivalent to 4.8% of the company's current Taiwanese output but consuming 11% of group capex over the construction window.

The data confirms what equipment suppliers telegraphed in fourth-quarter earnings: fab construction timelines stretched from 24 months to 33 months on average due to specialized labor shortages and permitting delays, while utilization rates at existing facilities slipped to 78% in the December quarter—the lowest since pandemic restocking ended. Applied Materials reported deferred tool deliveries worth $1.9 billion as customers requested installation delays, and ASML's backlog, while still €40 billion, saw nine EUV shipments pushed beyond 2025. The buildout continues, but the urgency cooled.

Operators should track fab utilization data monthly through the SEMI equipment book-to-bill ratio and watch for customer prepayments converting to actual tool orders. The gap between announced capacity and operational capacity matters more than headline counts—fourteen of the 27 facilities lack finalized equipment contracts, and eight have not broken ground despite announcement dates before mid-2024. The U.S. Commerce Department's first CHIPS Act disbursements, expected in Q2 2025, will clarify which projects have genuine capital commitment versus political theater.

The buildout represents $420 billion in announced capital against semiconductor industry revenue of $520 billion in 2024, an investment-to-sales ratio of 81% that has preceded every prior downturn since 1998.