The Union Cabinet approved two semiconductor manufacturing units representing cumulative investment exceeding ₹3,900 crore, the same day NITI Aayog published a ten-year roadmap projecting India's semiconductor value chain will reach $120 billion to $150 billion by 2035. The roadmap does not specify foundry nodes or committed capacity tonnage. It emphasizes assembly, testing, and chip design over fabrication, acknowledging India enters a market where Taiwan, South Korea, and the United States already command 85% of global logic wafer capacity.
The two approved units have not been named. Ministry sources indicated one focuses on outsourced assembly and test, the other on analog and power management integrated circuits. Neither will produce sub-seven-nanometer logic. India's semiconductor strategy since the ₹76,000 crore incentive program launched in December 2021 has attracted five projects, four of which remain in permitting or site preparation. Micron Technology's ₹22,500 crore assembly and test facility in Gujarat, announced June 2023, is the only project past foundation stage and targets 2025 commissioning. The NITI Aayog document calls for 20,000 additional semiconductor engineers by 2027 and partnerships with IITs to expand post-graduate research seats by 40% within three years.
The $150 billion figure assumes India captures 12-15% of global assembly, test, and packaging revenue and 8-10% of fabless design spending by the mid-2030s. That would require displacing incumbents in Malaysia, Vietnam, and China's Jiangsu corridor, where labor arbitrage has narrowed and supply-chain resilience clauses in US and EU procurement now favor jurisdictions with treaty-grade intellectual property frameworks. India currently holds under 3% of global ATMP market share. The roadmap projects the sector will employ 280,000 workers by 2032, up from an estimated 22,000 today, but does not model wage inflation or the retention cost of preventing talent migration to Samsung's Texas and TSMC's Arizona expansions, both of which are staffing from the same IIT graduate pools.
State-level competition is already visible. Gujarat, Karnataka, and Assam have each announced supplementary land grants and power tariff freezes for semiconductor investors. Tamil Nadu is preparing a ₹2,100 crore dedicated semiconductor park with pre-cleared environmental certificates, targeting announcements in the second quarter. The NITI roadmap recommends the central government prioritize four geographic clusters rather than diffuse incentives across fifteen states, but does not name the four. Without consolidation, infrastructure spending per facility will dilute, and no single cluster will achieve the supplier density that makes Taiwan's Hsinchu or South Korea's Giheung competitive at scale.
Operators should track two markers in the next six months: whether the unnamed ₹3,900 crore approvals break ground by September 2025, and whether NITI Aayog's follow-on technical committee publishes node-specific capacity targets by the third quarter. If neither occurs, the $150 billion projection remains an aspiration rather than a capitalized roadmap. The Indian government has committed ₹1.3 trillion across all manufacturing incentive schemes since 2020; semiconductor projects have drawn ₹98,600 crore in approvals but ₹14,200 crore in actual deployed capital.
Micron's Gujarat unit remains the reference case. If it commissions on schedule in late 2025 and reaches 75% utilization by 2027, it will validate the ATMP-first strategy and justify the state subsidy model. If it delays past the first quarter of 2026 or faces yield issues in the ramp, the five other approved projects will face tighter scrutiny from their foreign technology partners, most of whom are hedging India exposure against Vietnam and Malaysia expansions already underway.