Worldwide semiconductor fabrication equipment spending for 300mm wafers is projected to reach $172 billion by 2029, driven by artificial intelligence accelerator demand that has altered capex planning across Taiwan Semiconductor Manufacturing, Samsung Foundry, and Intel's process node roadmap. The forecast represents a sustained investment cycle rather than the boom-bust pattern that characterized memory expansions in 2017 and 2021.

The buildout reflects three converging factors. Hyperscale compute buyers including Microsoft, Meta, and ByteDance are signing multi-year wafer supply agreements that guarantee minimum volumes, removing demand volatility that previously made foundries cautious. Process node transitions to 3nm and 2nm require $20 billion to $25 billion per leading-edge fab, double the cost of equivalent 7nm facilities five years ago. Geographic diversification mandates from Washington, Brussels, and Tokyo are funding parallel capacity in Arizona, Dresden, and Kumamoto even as Taiwan remains the primary production center.

China's equipment investment from 2025 through 2027 is forecast to exceed ¥14 trillion ($96 billion at current exchange rates), while South Korea and Taiwan will each deploy over ¥10 trillion in the same window. The Chinese figure includes mature-node capacity at 28nm and above, which remains exempt from October 2023 export controls and serves automotive, industrial, and consumer markets. South Korea's spending concentrates on Samsung's foundry ambitions and SK Hynix's high-bandwidth memory lines for AI training clusters. Taiwan's allocation splits between TSMC's 2nm ramp in Hsinchu and its first overseas advanced packaging facility in Kumamoto, operational in late 2027.

The packaging and testing segment is seeing parallel expansion. ASE Technology, Amkor, and Samsung have announced Vietnam facilities in the past eleven months, attracted by labor costs 40% below China's Jiangsu province and proximity to Southeast Asian assembly hubs. Vietnam's industrial base already supports Foxconn and Pegatron operations, reducing ramp time for cleanroom construction. The shift matters because advanced packaging—chiplets, 2.5D interposers, hybrid bonding—now represents 18% to 22% of total silicon cost for AI accelerators, up from 8% three years ago.

Operators and allocators should track three near-term developments. TSMC's January 2025 capital expenditure guidance, expected January 16th, will indicate whether $36 billion to $40 billion remains the annual run rate or if customer prepayments push spending higher. Applied Materials and ASML report December-quarter results in mid-February; their forward bookings will show whether the $172 billion 2029 figure assumes current order rates or requires acceleration. China's Ministry of Industry and Information Technology is expected to release its 2025-2027 semiconductor investment plan by March 31st, clarifying which mature-node projects receive state bank financing and which face private funding requirements.

The $172 billion figure assumes no major process node delays and continued AI model scaling at the current 3.5x annual parameter growth rate, making it a floor estimate if training cluster buildouts accelerate rather than a ceiling if demand moderates.